306 search results - page 36 / 62 » Statistical Delay Modeling in Logic Design and Synthesis |
101
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DAC
2008
ACM
16 years 2 months ago
2008
ACM
This paper addresses the problem of computational error modeling and analysis. Choosing different word-lengths for each functional unit in hardware implementations of numerical al...
GLVLSI
2006
IEEE
15 years 8 months ago
2006
IEEE
Process variations have become a key concern of circuit designers because of their significant, yet hard to predict impact on performance and signal integrity of VLSI circuits. St...
107
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DATE
2005
IEEE
15 years 7 months ago
2005
IEEE
- The problem of determining lower bounds for the energy cost of a given nanoscale design is addressed via a complexity theory-based approach. This paper provides a theoretical fra...
166
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FCCM
2011
IEEE
14 years 5 months ago
2011
IEEE
— Recent progress in High-Level Synthesis (HLS) es has helped raise the abstraction level of FPGA programming. However implementation and performance evaluation of the HLS-genera...
ISCA
2007
IEEE
15 years 8 months ago
2007
IEEE
The ever increasing sizes of on-chip caches and the growing domination of wire delay necessitate significant changes to cache hierarchy design methodologies. Many recent proposal...