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» Statistical Modeling for Circuit Simulation
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103
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TCAD
2008
93views more  TCAD 2008»
15 years 22 days ago
Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion
Starting at the 65-nm node, stress engineering to improve the performance of transistors has been a major industry focus. An intrinsic stress source--shallow trench isolation (STI)...
Andrew B. Kahng, Puneet Sharma, Rasit Onur Topalog...
PADS
1998
ACM
15 years 5 months ago
Event History Based Sparse State Saving in Time Warp
This paper presents a sparse state saving scheme for Time Warp parallel discrete event simulation. The scheme bases the selection of the states to be recorded on the event history...
Francesco Quaglia
102
Voted
ICANN
2005
Springer
15 years 6 months ago
Building the Cerebellum in a Computer
Abstract. We have built a realistic computational model of the cerebellum. This model simulates the cerebellar cortex of the size 0.5mm×1mm consisting of several types of neurons,...
Tadashi Yamazaki, Shigeru Tanaka
78
Voted
ASPDAC
1999
ACM
100views Hardware» more  ASPDAC 1999»
15 years 5 months ago
Node Sampling Technique to Speed Up Probability-Based Power Estimation Methods
We propose a new technique called node sampling to speed up the probability-based power estimation methods. It samples and processes only a small portion of total nodes to estimat...
Hoon Choi, Hansoo Kim, In-Cheol Park, Seung Ho Hwa...
AIA
2006
15 years 2 months ago
Speeding Up Model-based Diagnosis by a Heuristic Approach to Solving SAT
Model-based diagnosis of technical systems requires both a simulation machinery and a logic calculus. The former is responsible for the system's behavior analysis, the latter...
Benno Stein, Oliver Niggemann, Theodor Lettmann