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» Statistical Modeling for Circuit Simulation
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CODES
2005
IEEE
15 years 6 months ago
A power estimation methodology for systemC transaction level models
Majority of existing works on system level power estimation have focused on the processor, while there are very few that address power consumption of peripherals in a SoC. With th...
Nagu R. Dhanwada, Ing-Chao Lin, Vijay Narayanan
80
Voted
DATE
2008
IEEE
91views Hardware» more  DATE 2008»
15 years 7 months ago
Integrated approach to energy harvester mixed technology modelling and performance optimisation
This paper presents an integrated approach to energy harvester modelling and performance optimisation where the complete mixed physical-domain energy harvester system (micro gener...
Leran Wang, Tom J. Kazmierski, Bashir M. Al-Hashim...
VLSID
2002
IEEE
160views VLSI» more  VLSID 2002»
16 years 1 months ago
PREDICTMOS MOSFET Model and its Application to Submicron CMOS Inverter Delay Analysis
Predictive delay analysis is presented for a representative CMOS inverter with submicron device size using PREDICTMOS MOSFET model. As against SPICE, which adopts a time consuming...
A. B. Bhattacharyya, Shrutin Ulman
94
Voted
ICCD
2001
IEEE
154views Hardware» more  ICCD 2001»
15 years 9 months ago
Performance Optimization By Wire and Buffer Sizing Under The Transmission Line Model
As the operating frequency increases to Giga Hertz and the rise time of a signal is less than or comparable to the time-of-flight delay of a line, it is necessary to consider the...
Tai-Chen Chen, Song-Ra Pan, Yao-Wen Chang
GLVLSI
2010
IEEE
183views VLSI» more  GLVLSI 2010»
15 years 2 months ago
Semi-analytical model for schottky-barrier carbon nanotube and graphene nanoribbon transistors
This paper describes a physics-based semi-analytical model for Schottky-barrier carbon nanotube (CNT) and graphene nanoribbon (GNR) transistors. The model includes the treatment o...
Xuebei Yang, Gianluca Fiori, Giuseppe Iannaccone, ...