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» Statistical Modeling for Circuit Simulation
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CRYPTO
2001
Springer
95views Cryptology» more  CRYPTO 2001»
15 years 5 months ago
Robustness for Free in Unconditional Multi-party Computation
We present a very efficient multi-party computation protocol unconditionally secure against an active adversary. The security is maximal, i.e., active corruption of up to t < n/...
Martin Hirt, Ueli M. Maurer
111
Voted
ISQED
2000
IEEE
91views Hardware» more  ISQED 2000»
15 years 5 months ago
Probabilistic Bottom-Up RTL Power Estimation
We address the problem of power estimation at the register-transfer level (RTL). At this level, the circuit is described in terms of a set of interconnected memory elements and co...
Ricardo Ferreira, A.-M. Trullemans, José C....
DAC
1997
ACM
15 years 4 months ago
SPIE: Sparse Partial Inductance Extraction
Extracting the inductance of complex interconnect topologies is a formidable task, and simulating the resulting dense partial inductance matrix is even more difficult. Furthermore...
Zhijiang He, Mustafa Celik, Lawrence T. Pileggi
ASPDAC
2005
ACM
131views Hardware» more  ASPDAC 2005»
15 years 2 months ago
Analysis of buffered hybrid structured clock networks
- This paper presents a novel approach for fast transient analysis of buffered hybrid structured clock networks. The new method applies structure reduction and relaxed hierarchical...
Yi Zou, Qiang Zhou, Yici Cai, Xianlong Hong, Sheld...
120
Voted
DAC
2008
ACM
16 years 1 months ago
Transistor level gate modeling for accurate and fast timing, noise, and power analysis
Current source based cell models are becoming a necessity for accurate timing and noise analysis at 65nm and below. Voltage waveform shapes are increasingly more difficult to repr...
S. Raja, F. Varadi, Murat R. Becer, Joao Geada