1459 search results - page 55 / 292 » Statistical Modeling for Circuit Simulation |
116
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EURODAC
1995
IEEE
15 years 3 months ago
1995
IEEE
We examine delay models used in VLSI circuit testing. Our study includes electrical-level simulation experiments with HSPICE. We show phenomena which signi cantly a ect the actual...
ITC
2003
IEEE
15 years 5 months ago
2003
IEEE
This paper describes a new post-silicon validation problem for diagnosing systematic timing errors. We illustrate the differences between timing validation and the traditional log...
WSC
1998
15 years 1 months ago
1998
This paper discusses how simulation is used to design new manufacturing systems and to improve the performance of existing ones. Topics to be discussed include: manufacturing issu...
112
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DAC
1997
ACM
15 years 3 months ago
1997
ACM
We propose a methodology for applying gate-level logic transformations to optimize power in digital circuits. Statistically simulated[14] switching information, gate delays, signa...
ISLPED
1997
ACM
15 years 4 months ago
1997
ACM
In this paper we present a methodology and techniques for generating cycle-accurate macro-models for RTlevel power analysis. The proposed macro-model predicts not only...