We study the problem of asymptotically reducing the runtime of serial computations with circuits of polynomial size. We give an algorithmic size-depth tradeoff for parallelizing ...
- Dynamic power consumption in CMOS circuits is usually estimated based on the number of signal transitions. However, when considering glitches, this is not accurate because narrow...
This paper is focused on estimating the quality of the sample mean from a steady-state simulation experiment with consideration of computational efficiency, memory requirement, an...
In this work we want to show the importance of visualization, interfaces and re-design techniques through 3D modeling, animations and VRML in the developing of the simulation game...
Reduction of an extracted netlist is an important pre-processing step for techniques such as model order reduction in the design and analysis of VLSI circuits. This paper describe...
Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Isma...