1459 search results - page 87 / 292 » Statistical Modeling for Circuit Simulation |
ICCAD
1994
IEEE
15 years 4 months ago
1994
IEEE
Abstract - Today's digital design systems are running out of steam, when it comes to meeting the challenges presented by simultaneous switching, power consumption and reliabil...
IJCNN
2000
IEEE
15 years 4 months ago
2000
IEEE
This paper presents a simple continuous analog hardware realization of the Random Neural Network (RNN) model. The proposed circuit uses the general principles resulting from the u...
DATE
2002
IEEE
15 years 4 months ago
2002
IEEE
Transistor tapering is a widely used technique applied to optimize the geometries of CMOS transistors in highperformance circuit design with a view to minimizing the delay of a FE...
INFOCOM
2000
IEEE
15 years 4 months ago
2000
IEEE
—In a reconfigurable network, lightpath connections can be dynamically changed to reflect changes in traffic conditions. This paper characterizes the gain in traffic capacity tha...
105
click to vote
ISLPED
1995
ACM
15 years 3 months ago
1995
ACM
We consider the problem of transistor sizing in a static CMOS layout to minimizethe power consumption of the circuit subject to a given delay constraint. Based on our characteriza...