6366 search results - page 85 / 1274 » Statistical Performance Modeling and Optimization |
ICCAD
1994
IEEE
15 years 4 months ago
1994
IEEE
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
140
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CASES
2006
ACM
15 years 6 months ago
2006
ACM
Developing an optimizing compiler for a newly proposed architecture is extremely difficult when there is only a simulator of the machine available. Designing such a compiler requ...
NIPS
2007
15 years 2 months ago
2007
Hierarchical penalization is a generic framework for incorporating prior information in the fitting of statistical models, when the explicative variables are organized in a hiera...
137
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NAA
2004
Springer
15 years 6 months ago
2004
Springer
In this paper, we develop a probabilistic model for estimation of the numbers of cache misses during the sparse matrix-vector multiplication (for both general and symmetric matrice...
ICIP
2004
IEEE
16 years 2 months ago
2004
IEEE
In the framework of a face verification system using local features and a Gaussian Mixture Model based classifier, we address the problem of non-frontal face verification (when on...