291 search results - page 3 / 59 » Statistical Power Estimation for FPGA |
TVLSI
2010
13 years 29 days ago
2010
In this paper, we present a low-power architectural synthesis system (LOPASS) for field-programmable gate-array (FPGA) designs with interconnect power estimation and optimization. ...
DAC
2007
ACM
14 years 7 months ago
2007
ACM
In 90-nm technology, dynamic power is still the largest power source in FPGAs [1], and signal glitches contribute a large portion of the dynamic power consumption. Previous powera...
FPL
2006
Springer
13 years 10 months ago
2006
Springer
This paper examines various activity estimation techniques in order to determine which are most appropriate for use in the context of field-programmable gate arrays (FPGAs). Speci...
DAC
2006
ACM
14 years 7 months ago
2006
ACM
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...
ISCAS
2002
IEEE
13 years 11 months ago
2002
IEEE
The evaluation of power consumption in complex digital systems is a hard task that normally requires long simulation time and complicated models. In this work, we obtain power con...