548 search results - page 10 / 110 » Statistical Timing Based Optimization using Gate Sizing |
ICCD
2004
IEEE
15 years 7 months ago
2004
IEEE
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...
DAC
2008
ACM
15 years 11 months ago
2008
ACM
Current source based cell models are becoming a necessity for accurate timing and noise analysis at 65nm and below. Voltage waveform shapes are increasingly more difficult to repr...
TCAD
2008
14 years 10 months ago
2008
Physical synthesis tools are responsible for achieving timing closure. Starting with 130nm designs, multiple cycles are required to cross the chip, making latch placement critical...
ICCAD
2006
IEEE
15 years 7 months ago
2006
IEEE
Ignoring the effect of simultaneous switching for logic gates causes silicon failures for high performance microprocessor designs. The main reason to omit this effect is the run...
BMCBI
2007
14 years 10 months ago
2007
Background: To infer homology and subsequently gene function, the Smith-Waterman (SW) algorithm is used to find the optimal local alignment between two sequences. When searching s...