548 search results - page 11 / 110 » Statistical Timing Based Optimization using Gate Sizing |
ICCAD
2006
IEEE
15 years 7 months ago
2006
IEEE
Statistical static timing analysis (SSTA) is emerging as a solution for predicting the timing characteristics of digital circuits under process variability. For computing the stat...
ISQED
2005
IEEE
15 years 3 months ago
2005
IEEE
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...
ASPDAC
2006
ACM
15 years 4 months ago
2006
ACM
With shrinking technology, the timing variation of a digital circuit is becoming the most important factor while designing a functionally reliable circuit. Gate sizing has emerged...
JCP
2008
14 years 10 months ago
2008
Processor is an important computing element in portable battery operated real time embedded system and it consumes most of the battery energy. Energy consumption, processor memory ...
ICCAD
2003
IEEE
15 years 7 months ago
2003
IEEE
The recent past has seen a tremendous increase in the size of design circuits that can be implemented in a single FPGA. These large design sizes significantly impact cycle time du...