548 search results - page 13 / 110 » Statistical Timing Based Optimization using Gate Sizing |
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
Leakage power is a serious concern in nanometer CMOS technologies. In this paper we focus on leakage reduction through automatic insertion of sleep transistors for power gating in...
DFT
2002
IEEE
15 years 3 months ago
2002
IEEE
We propose an algorithm for gate-delay fault diagnosis. It is based on the inject-and-evaluate paradigm [1], in which the fault site(s) are predicted through a series of injection...
COMCOM
2010
14 years 9 months ago
2010
We offer an analytical solution for the optimal frame size of the non-muting version of the Basic Frame Slotted ALOHA collision resolution protocol for RFID networks. Previous inv...
ASPDAC
2007
ACM
15 years 2 months ago
2007
ACM
Traditional timing variation reduction techniques are only able to decrease the gate delay variation by incurring a delay overhead. In this work, we propose novel and effective sp...
ICCAD
1993
IEEE
15 years 2 months ago
1993
IEEE
We have proposed an e cient measure to reduce the clock skew by assigning the clock network with variable branch widths. This measure has long been used for \H" clock tree. T...