548 search results - page 17 / 110 » Statistical Timing Based Optimization using Gate Sizing |
86
Voted
VLSISP
2008
14 years 10 months ago
2008
Each new semiconductor technology node brings smaller, faster transistors and smaller, slower wires. In particular, long interconnect wires in modern FPGAs now require rebuffering ...
ISSS
2002
IEEE
15 years 3 months ago
2002
IEEE
Software pipelining and unfolding are commonly used techniques to increase parallelism for DSP applications. However, these techniques expand the code size of the application sign...
DAC
1999
ACM
15 years 11 months ago
1999
ACM
Recently, several algorithms for interconnect optimization via repeater insertion and wire sizing have appeared based on the Elmore delay model. Using the Devgan noise metric [6] ...
IIWAS
2004
14 years 11 months ago
2004
Access to different and remote sources with heterogeneous formats is one of the most important challenges in Enterprise Information Integration. Even though there exists an increa...
ISQED
2008
IEEE
15 years 4 months ago
2008
IEEE
—Power and energy consumption has emerged as the premier and most constraining aspect in modern computational systems. Dynamic Voltage Scheduling (DVS) has been provably one of t...