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» Statistical Timing Based Optimization using Gate Sizing
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SAC
2002
ACM
14 years 9 months ago
Statistical properties of the simulated time horizon in conservative parallel discrete-event simulations
We investigate the universal characteristics of the simulated time horizon of the basic conservative parallel algorithm when implemented on regular lattices. This technique [1, 2]...
G. Korniss, M. A. Novotny, A. K. Kolakowska, H. Gu...
72
Voted
VLSID
2003
IEEE
103views VLSI» more  VLSID 2003»
15 years 10 months ago
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program
In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number ofconstraints. By intr...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
DATE
2005
IEEE
128views Hardware» more  DATE 2005»
15 years 3 months ago
Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits
Nanometer circuits are becoming increasingly susceptible to soft-errors due to alpha-particle and atmospheric neutron strikes as device scaling reduces node capacitances and suppl...
Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhij...
ICC
2009
IEEE
135views Communications» more  ICC 2009»
15 years 4 months ago
Block Detection of Multiple Symbol DPSK in a Statistically Unknown Time-Varying Channel
—We present a detection scheme for multiple-symbol DPSK for use in a statistically unknown time-varying channel. The scheme relies on a parametric representation of the timevaryi...
Nathan Ricklin, James R. Zeidler
ISQED
2009
IEEE
124views Hardware» more  ISQED 2009»
15 years 5 months ago
Revisiting the linear programming framework for leakage power vs. performance optimization
— This paper revisits and extends a general linear programming(LP) formulation to exploit multiple knobs such as multi-Lgate footprint-compatible libraries and post-layout Lgateb...
Kwangok Jeong, Andrew B. Kahng, Hailong Yao