548 search results - page 22 / 110 » Statistical Timing Based Optimization using Gate Sizing |
ICCAD
2006
IEEE
15 years 7 months ago
2006
IEEE
Statistical static timing analysis (SSTA) has become a key method for analyzing the effect of process variation in aggressively scaled CMOS technologies. Much research has focused...
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ICIP
2007
IEEE
15 years 4 months ago
2007
IEEE
This paper presents some techniques for efficient motion estimation (ME) implementation on fixed-point digital signal processor (DSP) for high resolution video coding. First, chal...
ICCAD
2000
IEEE
15 years 1 months ago
2000
IEEE
ct Static timing analysis has traditionally used the PERT method for identifying the critical path of a digital circuit. Due to the influence of the slope of a signal at a particul...
ICCAD
2006
IEEE
15 years 7 months ago
2006
IEEE
Parametric yield loss due to variability can be effectively reduced by both design-time optimization strategies and by adjusting circuit parameters to the realizations of variable...
ICCAD
2008
IEEE
15 years 7 months ago
2008
IEEE
Abstract— As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Compared to gate delays, wires are becoming increasing...