548 search results - page 59 / 110 » Statistical Timing Based Optimization using Gate Sizing |
88
Voted
GECCO
2008
Springer
15 years 1 months ago
2008
Springer
Single and multi-step time-series predictors were evolved for forecasting minimum bidding prices in a simulated supply chain management scenario. Evolved programs were allowed to ...
97
Voted
VLSID
2006
IEEE
16 years 26 days ago
2006
IEEE
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
97
Voted
ISPA
2004
Springer
15 years 5 months ago
2004
Springer
HPL is a parallel Linpack benchmark package widely adopted in massive cluster system performance test. On HPL data layout among processors, a law to determine block size NB theoret...
124
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FPGA
2007
ACM
15 years 6 months ago
2007
ACM
Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meet...
103
Voted
AAAI
2004
15 years 1 months ago
2004
Obtaining an accurate multiple alignment of protein sequences is a difficult computational problem for which many heuristic techniques sacrifice optimality to achieve reasonable r...