548 search results - page 5 / 110 » Statistical Timing Based Optimization using Gate Sizing |
ISPD
2003
ACM
15 years 3 months ago
2003
ACM
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
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ISPD
2012
ACM
13 years 5 months ago
2012
ACM
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
ICCAD
2002
IEEE
15 years 7 months ago
2002
IEEE
─ In this paper, we present Forge, an optimal algorithm for gate sizing using the Elmore delay model. The algorithm utilizes Lagrangian relaxation with a fast gradient-based pre-...
DAC
2005
ACM
15 years 11 months ago
2005
ACM
We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporat...
ISPD
1999
ACM
15 years 2 months ago
1999
ACM
- In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a path-based delay model to capture the timing c...