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ICCAD
2009
IEEE
152views Hardware» more  ICCAD 2009»
13 years 4 months ago
Adaptive sampling for efficient failure probability analysis of SRAM cells
In this paper, an adaptive sampling method is proposed for the statistical SRAM cell analysis. The method is composed of two components. One part is the adaptive sampler that manip...
Javid Jaffari, Mohab Anis
DATE
2005
IEEE
143views Hardware» more  DATE 2005»
13 years 8 months ago
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies
Operating frequency of a pipelined circuit is determined by the delay of the slowest pipeline stage. However, under statistical delay variation in sub-100nm technology regime, the...
Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay,...
DAC
2011
ACM
12 years 6 months ago
Rethinking memory redundancy: optimal bit cell repair for maximum-information storage
SRAM design has been a major challenge for nanoscale manufacturing technology. We propose a new bit cell repair scheme for designing maximum-information memory system (MIMS). Unli...
Xin Li
DATE
2007
IEEE
124views Hardware» more  DATE 2007»
14 years 23 days ago
Worst-case design and margin for embedded SRAM
An important aspect of Design for Yield for embedded SRAM is identifying the expected worst case behavior in order to guarantee that sufficient design margin is present. Previousl...
Robert C. Aitken, Sachin Idgunji
ICCAD
2009
IEEE
87views Hardware» more  ICCAD 2009»
13 years 4 months ago
Mitigation of intra-array SRAM variability using adaptive voltage architecture
SRAM cell design is driven by the need to satisfy static noise margin, write margin and read current margin (RCM) over all cells in the array in an energy-efficient manner. These ...
Ashish Kumar Singh, Ku He, Constantine Caramanis, ...