31 search results - page 3 / 7 » Statistical gate delay model for Multiple Input Switching |
ICCAD
2005
IEEE
14 years 3 months ago
2005
IEEE
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...
ASPDAC
2006
ACM
14 years 7 days ago
2006
ACM
As technology scales down, timing verification of digital integrated circuits becomes an increasingly challenging task due to the gate and wire variability. Therefore, statistical...
DAC
2006
ACM
14 years 7 months ago
2006
ACM
A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can a...
ISCAS
2008
IEEE
14 years 20 days ago
2008
IEEE
— This paper presents models for estimating the transition activity of signals at the output of adders in Field Programmable Gate Arrays (FPGAs), given only word-level measures o...
TCAD
2010
13 years 29 days ago
2010
Crosstalk faults have emerged as a significant mechanism for circuit failure. Long signal nets are of particular concern because they tend to have a higher coupling capacitance to...