246 search results - page 26 / 50 » Statistical gate sizing for timing yield optimization |
156
Voted
CODES
2010
IEEE
15 years 1 months ago
2010
IEEE
The impact of process variation in state of the art technology makes traditional (worst case) designs unnecessarily pessimistic, which translates to suboptimal designs in terms of...
161
Voted
DRR
2008
15 years 5 months ago
2008
Adaptive binarization is an important first step in many document analysis and OCR processes. This paper describes a fast adaptive binarization algorithm that yields the same qual...
102
Voted
DATE
2009
IEEE
15 years 10 months ago
2009
IEEE
—Negative Bias Temperature Instability (NBTI) is a significant reliability concern for nanoscale CMOS circuits. Its effects on circuit timing can be especially pronounced for ci...
107
Voted
FCCM
2008
IEEE
15 years 10 months ago
2008
IEEE
Power reduction is becoming more important as circuit size increases. This paper presents a tool called PowerCutter which employs accuracy-guaranteed word-length optimization to r...
134
Voted
ICCAD
2006
IEEE
16 years 17 days ago
2006
IEEE
Abstract— Design variability due to within-die and die-todie process variations has the potential to significantly reduce the maximum operating frequency and the effective yield...