246 search results - page 6 / 50 » Statistical gate sizing for timing yield optimization |
111
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ISQED
2010
IEEE
15 years 3 months ago
2010
IEEE
Circuit design under process variation can be formulated mathematically as a robust optimization problem with a yield constraint. Existing methods force designers to either resort...
ICCAD
2004
IEEE
15 years 10 months ago
2004
IEEE
Abstract— This paper presents a post-route, timingconstrained gate-sizing algorithm for crosstalk reduction. Gate-sizing has emerged as a practical and feasible method to reduce ...
124
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TCAD
2008
15 years 1 months ago
2008
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
134
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PATMOS
2007
Springer
15 years 8 months ago
2007
Springer
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
114
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ICCAD
2004
IEEE
15 years 10 months ago
2004
IEEE
— In deep sub-micron technologies, process variations can cause significant path delay and clock skew uncertainties thereby lead to timing failure and yield loss. In this paper,...