2286 search results - page 4 / 458 » Statistical timing analysis based on a timing yield model |
FPGA
2007
ACM
15 years 3 months ago
2007
ACM
Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re...
ICCAD
2005
IEEE
15 years 6 months ago
2005
IEEE
— As technology scales into the sub-90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as sta...
71
Voted
ASPDAC
2006
ACM
15 years 3 months ago
2006
ACM
Statistical timing analysis has been widely applied to predict the timing yield of VLSI circuits when process variations become significant. Existing statistical latch timing met...
69
Voted
DAC
2005
ACM
14 years 11 months ago
2005
ACM
Traditional corner analysis fails to guarantee a target yield for a given performance metric. However, recently proposed solutions, in the form of statistical timing analysis, whi...
ISQED
2007
IEEE
15 years 3 months ago
2007
IEEE
In nanometer regime, the effects of variations are having an increasing impact on the delay and power characteristics of devices as well as the yield of the circuit. Statistical t...