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73
Voted
DAC
2003
ACM
16 years 1 months ago
Statistical timing for parametric yield prediction of digital integrated circuits
Jochen A. G. Jess, K. Kalafala, Srinath R. Naidu, ...
116
Voted
DAC
2003
ACM
16 years 1 months ago
Death, taxes and failing chips
In the way they cope with variability, present-day methodologies are onerous, pessimistic and risky, all at the same time! Dealing with variability is an increasingly important as...
Chandu Visweswariah
90
Voted
DAC
2004
ACM
16 years 1 months ago
Statistical timing analysis based on a timing yield model
Starting from a model of the within-die systematic variations using principal components analysis, a model is proposed for estimation of the parametric yield, and is then applied ...
Farid N. Najm, Noel Menezes
FPGA
2007
ACM
142views FPGA» more  FPGA 2007»
15 years 6 months ago
Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis
Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re...
N. Pete Sedcole, Peter Y. K. Cheung
DAC
2004
ACM
15 years 5 months ago
Parametric yield estimation considering leakage variability
Leakage current has become a stringent constraint in today’s processor designs in addition to traditional constraints on frequency. Since leakage current exhibits a strong inver...
Rajeev R. Rao, Anirudh Devgan, David Blaauw, Denni...