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QEST
2006
IEEE
15 years 6 months ago
Compositional Performability Evaluation for STATEMATE
Abstract— This paper reports on our efforts to link an industrial state-of-the-art modelling tool to academic state-of-the-art analysis algorithms. In a nutshell, we enable timed...
Eckard Böde, Marc Herbstritt, Holger Hermanns...
222
Voted
RTAS
2011
IEEE
14 years 4 months ago
FPZL Schedulability Analysis
— This paper presents the Fixed Priority until Zero Laxity (FPZL) scheduling algorithm for multiprocessor realtime systems. FPZL is similar to global fixed priority preemptive sc...
Robert I. Davis, Alan Burns
HICSS
1995
IEEE
109views Biometrics» more  HICSS 1995»
15 years 4 months ago
The architecture of an optimistic CPU: the WarpEngine
The architecture for a shared memory CPU is described. The CPU allows for parallelism down to the level of single instructions and is tolerant of memory latency. All executable in...
John G. Cleary, Murray Pearson, Husam Kinawi
ICDCS
1997
IEEE
15 years 5 months ago
Connection Admission Control for Hard Real-Time Communication in ATM Networks
Connection Admission Control (CAC) is needed in ATM networks to provide Quality of Service (QoS) guarantees to real-time connections. This paper presents a CAC scheme based on a b...
Qin Zheng, Tetsuya Yokotani, Tatsuki Ichihashi, Ya...
89
Voted
SPAA
1998
ACM
15 years 5 months ago
Fast Set Operations Using Treaps
We present parallel algorithms for union, intersection and difference on ordered sets using random balanced binary trees (treaps [26]). For two sets of size n and m (m ≤ n) the...
Guy E. Blelloch, Margaret Reid-Miller