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LICS
2007
IEEE
15 years 10 months ago
The Cost of Punctuality
In an influential paper titled “The Benefits of Relaxing Punctuality” [2], Alur, Feder, and Henzinger introduced Metric Interval Temporal Logic (MITL) as a fragment of the r...
Patricia Bouyer, Nicolas Markey, Joël Ouaknin...
QSIC
2007
IEEE
15 years 10 months ago
Verifying Noninterference in a Cyber-Physical System The Advanced Electric Power Grid
The advanced electric power grid is a complex real-time system having both Cyber and Physical components. While each component may function correctly, independently, their composi...
Yan Sun, Bruce M. McMillin, Xiaoqing Frank Liu, Da...
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Voted
DATE
2006
IEEE
111views Hardware» more  DATE 2006»
15 years 10 months ago
Functional test generation using property decompositions for validation of pipelined processors
Functional validation is a major bottleneck in pipelined processor design. Simulation using functional test vectors is the most widely used form of processor validation. While exi...
Heon-Mo Koo, Prabhat Mishra
ASPDAC
2007
ACM
139views Hardware» more  ASPDAC 2007»
15 years 7 months ago
Deeper Bound in BMC by Combining Constant Propagation and Abstraction
ound in BMC by Combining Constant Propagation and Abstraction Roy Armoni, Limor Fix1 , Ranan Fraer1 , Tamir Heyman1,3 , Moshe Vardi2 , Yakir Vizel1 , Yael Zbar1 1 Logic and Validat...
Roy Armoni, Limor Fix, Ranan Fraer, Tamir Heyman, ...
ICCD
1995
IEEE
109views Hardware» more  ICCD 1995»
15 years 7 months ago
Verifying the performance of the PCI local bus using symbolic techniques
Symbolic model checking is a successful technique for checking properties of large finite-state systems. This method has been used to verify a number of real-world hardware desig...
Sérgio Vale Aguiar Campos, Edmund M. Clarke...