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» Storage allocation for embedded processors
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CASES
2001
ACM
15 years 3 months ago
Patchable instruction ROM architecture
Increased systems level integration has meant the movement of many traditionally off chip components onto a single chip including a processor, instruction storage, data path, and ...
Timothy Sherwood, Brad Calder
DATE
2010
IEEE
204views Hardware» more  DATE 2010»
15 years 4 months ago
Assertion-based verification of RTOS properties
— Today, mobile and embedded real time systems have to cope with the migration and allocation of multiple software tasks running on top of a real time operating system (RTOS) res...
Marcio F. S. Oliveira, Henning Zabel, Wolfgang M&u...
RTAS
2000
IEEE
15 years 4 months ago
Evaluating Policies and Mechanisms for Supporting Embedded, Real-Time Applications with CORBA 3.0
To be an effective platform for performance-sensitive realtime systems, commercial-off-the-shelf (COTS) distributed object computing (DOC) middleware must support application qual...
Carlos O'Ryan, Douglas C. Schmidt, Fred Kuhns, Mar...
RTAS
1998
IEEE
15 years 4 months ago
Managing Memory Requirements in the Synthesis of Real-Time Systems from Processing Graphs
In the past, environmental restrictions on size, weight, and power consumption have severely limited both the processing and storage capacity of embedded signal processing systems...
Steve Goddard, Kevin Jeffay
DAC
2009
ACM
15 years 4 months ago
Heterogeneous code cache: using scratchpad and main memory in dynamic binary translators
Dynamic binary translation (DBT) can be used to address important issues in embedded systems. DBT systems store translated code in a software-managed code cache. Unlike general-pu...
José Baiocchi, Bruce R. Childers