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» Storage allocation for embedded processors
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GLVLSI
2007
IEEE
162views VLSI» more  GLVLSI 2007»
13 years 10 months ago
Utilizing custom registers in application-specific instruction set processors for register spills elimination
Application-specific instruction set processor (ASIP) has become an important design choice for embedded systems. It can achieve both high flexibility offered by the base processo...
Hai Lin, Yunsi Fei
TVLSI
2002
94views more  TVLSI 2002»
13 years 5 months ago
A network flow approach to memory bandwidth utilization in embedded DSP core processors
This paper presents a network flow approach to solving the register binding and allocation problem for multiword memory access DSP processors. In recently announced DSP processors,...
Catherine H. Gebotys
SAC
2008
ACM
13 years 5 months ago
Exploiting program cyclic behavior to reduce memory latency in embedded processors
In this work we modify the conventional row buffer allocation mechanism used in DDR2 SDRAM banks to improve average memory latency and overall processor performance. Our method as...
Ehsan Atoofian, Amirali Baniasadi
IEEEPACT
2002
IEEE
13 years 11 months ago
A Framework for Parallelizing Load/Stores on Embedded Processors
Many modern embedded processors (esp. DSPs) support partitioned memory banks (also called X-Y memory or dual bank memory) along with parallel load/store instructions to achieve co...
Xiaotong Zhuang, Santosh Pande, John S. Greenland ...
ISSS
1995
IEEE
100views Hardware» more  ISSS 1995»
13 years 9 months ago
Optimal code generation for embedded memory non-homogeneous register architectures
This paper examines the problem of code-generation for expression trees on non-homogeneous register set architectures. It proposes and proves the optimality of an O(n) algorithm f...
Guido Araujo, Sharad Malik