Sciweavers

47 search results - page 3 / 10
» Strategies for Branch Target Buffers
Sort
View
ISCA
1995
IEEE
109views Hardware» more  ISCA 1995»
15 years 3 months ago
Next Cache Line and Set Prediction
Accurate instruction fetch and branch prediction is increasingly important on today’s wide-issue architectures. Fetch prediction is the process of determining the next instructi...
Brad Calder, Dirk Grunwald
MICRO
1995
IEEE
140views Hardware» more  MICRO 1995»
15 years 3 months ago
A system level perspective on branch architecture performance
Accurate instruction fetch and branch prediction is increasingly important on today’s wide-issue architectures. Fetch prediction is the process of determining the next instructi...
Brad Calder, Dirk Grunwald, Joel S. Emer
IEEEPACT
2000
IEEE
15 years 4 months ago
Dynamic Branch Prediction for a VLIW Processor
This paper describes the design of a dynamic branchpredictorfor a VLIW processor. The developed branch predictor predicts the direction of a branch, i.e., taken or not taken, and ...
Jan Hoogerbrugge
ISCA
2007
IEEE
115views Hardware» more  ISCA 2007»
15 years 6 months ago
VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization
Indirect branches have become increasingly common in modular programs written in modern object-oriented languages and virtualmachine based runtime systems. Unfortunately, the pred...
Hyesoon Kim, José A. Joao, Onur Mutlu, Chan...
CDES
2006
89views Hardware» more  CDES 2006»
15 years 1 months ago
Autonomous Instruction Memory Equipped with Dynamic Branch Handling Capability
Memory accesses have always been a speed-limiting factor, and memory bandwidth has always been an intensively contended scarce resource. Nevertheless, with recent pervasive emergen...
Hui-Chin Yang, Chung-Ping Chung