585 search results - page 59 / 117 » Strategy Logic |
ICPP
2005
IEEE
15 years 7 months ago
2005
IEEE
Automatic pattern search in event traces is a powerful method to identify performance problems in parallel applications. We demonstrate that knowledge about the virtual topology, ...
ISQED
2003
IEEE
15 years 7 months ago
2003
IEEE
A structurally testable delay fault might become untestable in the functional mode of the circuit due to logic or timing constraints or both. Experimental data suggests that there...
FPL
2003
Springer
15 years 7 months ago
2003
Springer
This paper introduces the notion of a software decelerator, to be used in logic-centric system architectures. Functions are offloaded from logic to a processor, accepting a speed ...
111
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CADE
1998
Springer
15 years 6 months ago
1998
Springer
Abstract. We present a theorem proving environment for the development of reliable and efficient group communication systems. Our approach makes methods of automated deduction appl...
102
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VTS
1996
IEEE
15 years 6 months ago
1996
IEEE
Designing a testable circuit is often a two step process. First, the circuit is designed to conform to the functional specifications. Then, the testability aspects are added. By t...