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ISPA
2007
Springer
15 years 11 months ago
Parallelization Strategies for the Points of Interests Algorithm on the Cell Processor
The Cell processor is a typical example of a heterogeneous multiprocessor-on-chip architecture that uses several levels of parallelism to deliver high performance. Closing the gap ...
Tarik Saidani, Lionel Lacassagne, Samir Bouaziz, T...
ISCAS
2006
IEEE
163views Hardware» more  ISCAS 2006»
15 years 11 months ago
ASIC hardware implementation of the IDEA NXT encryption algorithm
— Symmetric-key block ciphers are often used to provide data confidentiality with low complexity, especially in the case of dedicated hardware implementations. IDEA NXT is a nov...
Marco Macchetti, Wenyu Chen
CHES
2003
Springer
247views Cryptology» more  CHES 2003»
15 years 10 months ago
Very Compact FPGA Implementation of the AES Algorithm
Abstract. In this paper a compact FPGA architecture for the AES algorithm with 128-bit key targeted for low-cost embedded applications is presented. Encryption, decryption and key ...
Pawel Chodowiec, Kris Gaj
DATE
2008
IEEE
148views Hardware» more  DATE 2008»
15 years 11 months ago
Automated Dynamic Throughput-constrained Structural-level Pipelining in Streaming Applications
Stream processing applications such as image signal processing demand high throughput. However, customers increasingly demand runtime flexibility in their designs, which cannot b...
Mark Muir, Tughrul Arslan, Iain Lindsay
MMNS
2004
161views Multimedia» more  MMNS 2004»
15 years 6 months ago
Adaptive Video Streaming in Presence of Wireless Errors
Real-time video streaming with rate adaptation to network load/congestion represents an efficient solution to its coexistence with conventional TCP data services. Naturally, the st...
Guang Yang 0001, Mario Gerla, Medy Sanadidi