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HIPC
2000
Springer
15 years 1 months ago
Instruction Level Distributed Processing
Within two or three technology generations, processor architects will face a number of major challenges. Wire delays will become critical, and power considerations will temper the ...
James E. Smith
174
Voted
TON
2010
192views more  TON 2010»
14 years 5 months ago
Delay analysis for wireless networks with single hop traffic and general interference constraints
We consider a class of wireless networks with general interference constraints on the set of links that can be served simultaneously at any given time. We restrict the traffic to b...
Gagan Raj Gupta, Ness B. Shroff
88
Voted
VLSID
2005
IEEE
147views VLSI» more  VLSID 2005»
15 years 10 months ago
Memory-Centric Motion Estimator
In the streaming video processing domain, the only way to meet strict performance and quality requirements and yet to provide the area- and power-wise optimal platform is to apply...
Aleksandar Beric, Ramanathan Sethuraman, Jef L. va...
74
Voted
DCC
2002
IEEE
15 years 9 months ago
PPMexe: PPM for Compressing Software
With the emergence of software delivery platforms such as Microsoft's .NET, code compression has become one of the core enabling technologies strongly affecting system perfor...
Milenko Drinic, Darko Kirovski
SSDBM
2008
IEEE
150views Database» more  SSDBM 2008»
15 years 4 months ago
Summarizing Two-Dimensional Data with Skyline-Based Statistical Descriptors
Much real data consists of more than one dimension, such as financial transactions (eg, price × volume) and IP network flows (eg, duration × numBytes), and capture relationship...
Graham Cormode, Flip Korn, S. Muthukrishnan, Dives...