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ISMVL
2010
IEEE
188views Hardware» more  ISMVL 2010»
15 years 2 months ago
MDGs Reduction Technique Based on the HOL Theorem Prover
—Multiway Decision Graphs (MDGs) subsume Binary Decision Diagrams (BDDs) and extend them by a first-order formulae suitable for model checking of data path circuits. In this pap...
Sa'ed Abed, Otmane Aït Mohamed
WSC
1998
14 years 11 months ago
Effective Implementation of Cycle Time Reduction Strategies for Semiconductor Back-end Manufacturing
Using discrete-event simulation models, a study was conducted to evaluate the current production practices of a high-volume semiconductor back-end operation. The overall goal was ...
Joerg Domaschke, Steven Brown, Jennifer Robinson, ...
ENTCS
2007
144views more  ENTCS 2007»
14 years 9 months ago
Partial Order Reduction for Rewriting Semantics of Programming Languages
Software model checkers are typically language-specific, require substantial development efforts, and are hard to reuse for other languages. Adding partial order reduction (POR)...
Azadeh Farzan, José Meseguer
DATE
2007
IEEE
80views Hardware» more  DATE 2007»
15 years 4 months ago
Microarchitecture floorplanning for sub-threshold leakage reduction
Lateral heat conduction between modules affects the temperature profile of a floorplan, affecting the leakage power of individual blocks which increasingly is becoming a larger ...
Hushrav Mogal, Kia Bazargan
DAC
2009
ACM
15 years 1 months ago
Reduction techniques for synchronous dataflow graphs
The Synchronous Dataflow (SDF) model of computation is popular for modelling the timing behaviour of real-time embedded hardware and software systems and applications. It is an es...
Marc Geilen