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DAC
1999
ACM
15 years 2 months ago
Circuit Complexity Reduction for Symbolic Analysis of Analog Integrated Circuits
This paper presents a method to reduce the complexity of a linear or linearized (small-signal) analog circuit. The reduction technique, based on quality-error ranking, can be used...
Walter Daems, Georges G. E. Gielen, Willy M. C. Sa...
JIPS
2010
107views more  JIPS 2010»
14 years 4 months ago
Incremental Model-based Test Suite Reduction with Formal Concept Analysis
Test scenarios can be derived based on some system models for requirements validation purposes. Model-based test suite reduction aims to provide a smaller set of test scenarios whi...
Pin Ng, Richard Y. K. Fung, Ray W. M. Kong
ICCAD
2006
IEEE
100views Hardware» more  ICCAD 2006»
15 years 6 months ago
Faster, parametric trajectory-based macromodels via localized linear reductions
— Trajectory-based methods offer an attractive methodology for automated, on-demand generation of macromodels for custom circuits. These models are generated by sampling the stat...
Saurabh K. Tiwary, Rob A. Rutenbar
ETS
2007
IEEE
91views Hardware» more  ETS 2007»
15 years 4 months ago
PPM Reduction on Embedded Memories in System on Chip
This paper summarizes advanced test patterns designed to target dynamic and time-related faults caused by new defect mechanisms in deep-submicron memory technologies. Such tests a...
Said Hamdioui, Zaid Al-Ars, Javier Jiménez,...
SPIN
2005
Springer
15 years 3 months ago
Improving Spin's Partial-Order Reduction for Breadth-First Search
We describe an improvement of the partial-order reduction algorithm for breadth-first search which was introduced in Spin version 4.0. Our improvement is based on the algorithm by...
Dragan Bosnacki, Gerard J. Holzmann