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ISCA
2010
IEEE
340views Hardware» more  ISCA 2010»
15 years 9 months ago
Necromancer: enhancing system throughput by animating dead cores
Aggressive technology scaling into the nanometer regime has led to a host of reliability challenges in the last several years. Unlike onchip caches, which can be efficiently prot...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
160
Voted
ASPLOS
2010
ACM
15 years 7 months ago
Micro-pages: increasing DRAM efficiency with locality-aware data placement
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...
Kshitij Sudan, Niladrish Chatterjee, David Nellans...
CLA
2007
15 years 5 months ago
An FDP-Algorithm for Drawing Lattices
In this work we want to discuss an algorithm for drawing line diagrams of lattices based on force directed placement (FDP). This widely used technique in graph drawing introduces f...
Christian Zschalig
ATAL
2010
Springer
15 years 5 months ago
Stackelberg vs. Nash in security games: interchangeability, equivalence, and uniqueness
There has been significant recent interest in game theoretic approaches to security, with much of the recent research focused on utilizing the leader-follower Stackelberg game mod...
Zhengyu Yin, Dmytro Korzhyk, Christopher Kiekintve...
IWCMC
2010
ACM
15 years 1 months ago
Dynamic load balancing and throughput optimization in 3GPP LTE networks
Load imbalance that deteriorates the system performance is a severe problem existing in 3GPP LTE networks. To deal with this problem, we propose in this paper a load balancing fra...
Hao Wang, Lianghui Ding, Ping Wu, Zhiwen Pan, Nan ...
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