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DATE
2006
IEEE
108views Hardware» more  DATE 2006»
15 years 10 months ago
Scheduling under resource constraints using dis-equations
Scheduling is an important step in high-level synthesis (HLS). In our tool, we perform scheduling in two steps: coarse-grain scheduling, in which we take into account the whole co...
Hadda Cherroun, Alain Darte, Paul Feautrier
DATE
2006
IEEE
86views Hardware» more  DATE 2006»
15 years 10 months ago
Synthesis of system verilog assertions
In recent years, Assertion-Based Verification is being widely accepted as a key technology in the pre-silicon validation of system-on-chip(SOC) designs. The System Verilog langua...
Sayantan Das, Rizi Mohanty, Pallab Dasgupta, P. P....
DDECS
2006
IEEE
88views Hardware» more  DDECS 2006»
15 years 10 months ago
Minimization of Large State Spaces using Symbolic Branching Bisimulation
Abstract: Bisimulations in general are a powerful concept to minimize large finite state systems regarding some well-defined observational behavior. In contrast to strong bisimul...
Ralf Wimmer, Marc Herbstritt, Bernd Becker
ICALT
2006
IEEE
15 years 10 months ago
Adaptive Learning Objects Sequencing for Competence-Based Learning
Lifelong learning refers to the activities people perform throughout their life to improve their competence in a particular field. Although adaptive educational hypermedia systems...
Pythagoras Karampiperis, Demetrios G. Sampson
118
Voted
IRI
2006
IEEE
15 years 10 months ago
Replacing full rectangles by dense rectangles: Concept lattices and attribute implications
— Maximal full rectangles in tabular data are useful in several areas of data engineering. This paper presents a survey of results in which we replace “full rectangles” by ...
Radim Belohlávek, Vilém Vychodil