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ASPDAC
2004
ACM
106views Hardware» more  ASPDAC 2004»
15 years 3 months ago
A novel memory size model for variable-mapping in system level design
— It is predicted that 70% of the chip area will be occupied by memories in future system-onchips. The minimization of on-chip memory hence becomes increasingly important for cos...
Lukai Cai, Haobo Yu, Daniel Gajski
ICPP
2000
IEEE
15 years 2 months ago
Issues in Designing and Implementing a Scalable Virtual Interface Architecture
The Virtual Interface Architecture brings the benefits of low latency User-level Networking to a cluster environment. With an increasing number of communication channels created ...
Shailabh Nagar, Anand Sivasubramaniam, Jorge Rodri...
INFOCOM
2000
IEEE
15 years 2 months ago
Datagram Routing Algorithm for LEO Satellite Networks
Abstract—Satellite networks provide global coverage and support a wide range of services. Low Earth Orbit (LEO) satellites provide short round-trip delays and are becoming increa...
Eylem Ekici, Ian F. Akyildiz, Michael D. Bender
MICRO
2010
IEEE
154views Hardware» more  MICRO 2010»
14 years 7 months ago
Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory
High density memory is becoming more important as many execution streams are consolidated onto single chip many-core processors. DRAM is ubiquitous as a main memory technology, but...
Jeffrey Stuecheli, Dimitris Kaseridis, Hillery C. ...
DAC
2002
ACM
15 years 11 months ago
An integer linear programming based approach for parallelizing applications in On-chip multiprocessors
With energy consumption becoming one of the first-class optimization parameters in computer system design, compilation techniques that consider performance and energy simultaneous...
Ismail Kadayif, Mahmut T. Kandemir, Ugur Sezer