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115
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CISIS
2008
IEEE
15 years 10 months ago
On the Potential of NoC Virtualization for Multicore Chips
As the end of Moores-law is on the horizon, power becomes a limiting factor to continuous increases in performance gains for single-core processors. Processor engineers have shifte...
Jose Flich, Samuel Rodrigo, José Duato, Tho...
143
Voted
ICS
2005
Tsinghua U.
15 years 9 months ago
Disk layout optimization for reducing energy consumption
Excessive power consumption is becoming a major barrier to extracting the maximum performance from high-performance parallel systems. Therefore, techniques oriented towards reduci...
Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir
168
Voted
TCOS
2010
14 years 10 months ago
Green Secure Processors: Towards Power-Efficient Secure Processor Design
With the increasing wealth of digital information stored on computer systems today, security issues have become increasingly important. In addition to attacks targeting the softwar...
Siddhartha Chhabra, Yan Solihin
196
Voted
EUROPAR
2011
Springer
14 years 3 months ago
A Bit-Compatible Parallelization for ILU(k) Preconditioning
Abstract. ILU(k) is a commonly used preconditioner for iterative linear solvers for sparse, non-symmetric systems. It is often preferred for the sake of its stability. We present T...
Xin Dong 0004, Gene Cooperman
141
Voted
VLSID
2001
IEEE
164views VLSI» more  VLSID 2001»
16 years 4 months ago
An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das