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» Subject Reduction of Logic Programs as Proof-Theoretic Prope...
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FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
15 years 6 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson
PPDP
2004
Springer
15 years 2 months ago
Nominal rewriting systems
We present a generalisation of first-order rewriting which allows us to deal with terms involving binding operations in an elegant and practical way. We use a nominal approach to...
Maribel Fernández, Murdoch Gabbay, Ian Mack...
ICFP
2005
ACM
15 years 9 months ago
Types with semantics: soundness proof assistant
We present a parametric Hoare-like logic for computer-aided reasoning about typeable properties of functional programs. The logic is based on the concept of a specialised assertio...
Olha Shkaravska
MP
2011
14 years 9 days ago
An interior-point piecewise linear penalty method for nonlinear programming
We present an interior-point penalty method for nonlinear programming (NLP), where the merit function consists of a piecewise linear penalty function (PLPF) and an 2-penalty functi...
Lifeng Chen, Donald Goldfarb
73
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ECOOP
1998
Springer
15 years 1 months ago
An Imperative, First-Order Calculus with Object Extension
This paper presents an imperative object calculus designed to support class-based programming via a combination of extensible objects and encapsulation. This calculus simplifies th...
Viviana Bono, Kathleen Fisher