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FCCM
2002
IEEE
146views VLSI» more  FCCM 2002»
15 years 8 months ago
Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems
Several projects have developed compiler tools that translate high-level languages down to hardware description languages for mapping onto FPGAbased reconfigurable computers. Thes...
Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker...
JUCS
2008
187views more  JUCS 2008»
15 years 3 months ago
Semantic Information in Medical Information Systems: Utilization of Text Mining Techniques to Analyze Medical Diagnoses
: Most information in Hospitals is still only available in text format and the amount of this data is immensely increasing. Consequently, text mining is an essential area of medica...
Andreas Holzinger, Regina Geierhofer, Felix Mö...
161
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ENTCS
2007
168views more  ENTCS 2007»
15 years 3 months ago
Bytecode Rewriting in Tom
In this paper, we present a term rewriting based library for manipulating Java bytecode. We define a mapping from bytecode programs to algebraic terms, and we use Tom, an extensi...
Emilie Balland, Pierre-Etienne Moreau, Antoine Rei...
CDC
2010
IEEE
123views Control Systems» more  CDC 2010»
14 years 10 months ago
Causal observability of nonlinear time-delay systems with unknown inputs
This paper investigates the problem of causal observability of the states and unknown inputs of nonlinear time-delay systems. Using the theory of non-commutative rings, the nonline...
Gang Zheng, Jean-Pierre Barbot, Driss Boutat, Thie...
DFT
1998
IEEE
78views VLSI» more  DFT 1998»
15 years 8 months ago
A System for Evaluating On-Line Testability at the RT-level
This paper presents a system to evaluate the testability of an on-line testable circuit. The system operates at the RT-level, before the logic synthesis step, and allows for an ex...
Silvia Chiusano, Fulvio Corno, Matteo Sonza Reorda...