37 search results - page 7 / 8 » Subthreshold leakage modeling and reduction techniques |
Publication
With the technology moving into the deep sub-100nm region, the increase of leakage power consumption necessitates more aggressive power reduction techniques. Power gating is a prom...
ICCD
2005
IEEE
14 years 3 months ago
2005
IEEE
: Power consumption in datapath modules due to redundant switching is an important design concern for high-performance applications. Operand isolation schemes are adopted to reduce...
DAC
2002
ACM
14 years 7 months ago
2002
ACM
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
ASPDAC
2004
ACM
13 years 11 months ago
2004
ACM
— Reducing the ever-growing leakage power is critical to power efficient designs. Leakage reduction techniques such as power-gating using sleep transistor insertion introduces la...
PATMOS
2007
Springer
14 years 12 days ago
2007
Springer
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...