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118
Voted
ISLPED
2003
ACM
113views Hardware» more  ISLPED 2003»
15 years 9 months ago
Reducing power density through activity migration
Power dissipation is unevenly distributed in modern microprocessors leading to localized hot spots with significantly greater die temperature than surrounding cooler regions. Exc...
Seongmoo Heo, Kenneth C. Barr, Krste Asanovic
139
Voted
GLVLSI
2002
IEEE
106views VLSI» more  GLVLSI 2002»
15 years 8 months ago
A low power direct digital frequency synthesizer with 60 dBc spectral purity
We present a low-power sine-output Direct Digital Frequency Synthesizer (DDFS) realized in 0.18 µm CMOS that achieves 60 dBc spectral purity from DC to the Nyquist frequency. No ...
J. M. Pierre Langlois, Dhamin Al-Khalili
120
Voted
GLOBECOM
2007
IEEE
15 years 10 months ago
Performance Analysis of V-BLAST with Optimum Power Allocation
—Comprehensive performance analysis of the unordered V-BLAST algorithm with various power allocation strategies is presented, which makes use of analytical tools and resorts to M...
Victoria Kostina, Sergey Loyka
143
Voted
GLVLSI
1998
IEEE
122views VLSI» more  GLVLSI 1998»
15 years 8 months ago
Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding
With the increased clock frequency of modern, high-performance processors over 500 MHz, in some cases, limiting the power dissipation has become the most stringent design target. ...
Luca Benini, Giovanni De Micheli, Alberto Macii, E...
126
Voted
FPGA
2006
ACM
111views FPGA» more  FPGA 2006»
15 years 7 months ago
FPGA clock network architecture: flexibility vs. area and power
This paper examines the tradeoffs between flexibility, area, and power dissipation of programmable clock networks for FieldProgrammable Gate Arrays (FPGA's). The paper begins...
Julien Lamoureux, Steven J. E. Wilton