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CASES
2001
ACM
13 years 10 months ago
A system-on-a-chip lock cache with task preemption support
Intertask/interprocess synchronization overheads may be significant in a multiprocessor-shared memory System-on-a-Chip implementation. These overheads are observed in terms of loc...
Bilge Saglam Akgul, Jaehwan Lee, Vincent John Moon...
ICPP
1993
IEEE
13 years 10 months ago
Scalability Study of the KSR-1
Scalability of parallel architectures is an interesting area of current research. Shared memory parallel programming is attractive stemming from its relative ease in transitioning...
Umakishore Ramachandran, Gautam Shah, Ravi Kumar, ...
ISSAC
2007
Springer
162views Mathematics» more  ISSAC 2007»
14 years 15 days ago
Multiprocessed parallelism support in ALDOR on SMPs and multicores
We report on a high-level categorical parallel framework, written in the Aldor language, to support high-performance computer algebra on symmetric multi-processors and multicore p...
Marc Moreno Maza, Ben Stephenson, Stephen M. Watt,...
DAC
2008
ACM
14 years 7 months ago
Latency and bandwidth efficient communication through system customization for embedded multiprocessors
We present a cross-layer customization methodology for latency and bandwidth efficient inter-core communication in embedded multiprocessors. The methodology integrates compiler, o...
Chenjie Yu, Peter Petrov
SC
1995
ACM
13 years 10 months ago
Lazy Release Consistency for Hardware-Coherent Multiprocessors
Release consistency is a widely accepted memory model for distributed shared memory systems. Eager release consistency represents the state of the art in release consistent protoc...
Leonidas I. Kontothanassis, Michael L. Scott, Rica...