Sciweavers

465 search results - page 57 / 93
» Supporting Architectural Restructuring by Analyzing Feature ...
Sort
View
DSD
2009
IEEE
111views Hardware» more  DSD 2009»
15 years 6 months ago
Robustness Check for Multiple Faults Using Formal Techniques
Feature sizes in VLSI circuits are steadily shrinking. This results in increasing susceptibility to soft errors, e.g. due to environmental radiation. Precautions against soft error...
Stefan Frehse, Görschwin Fey, André S&...
CODES
2001
IEEE
15 years 3 months ago
Evaluating register file size in ASIP design
Interest in synthesis of Application Specific Instruction Set Processors or ASIPs has increased considerably and a number of methodologies have been proposed for ASIP design. A ke...
Manoj Kumar Jain, Lars Wehmeyer, Stefan Steinke, P...
BMCBI
2006
141views more  BMCBI 2006»
14 years 12 months ago
Visual setup of logical models of signaling and regulatory networks with ProMoT
Background: The analysis of biochemical networks using a logical (Boolean) description is an important approach in Systems Biology. Recently, new methods have been proposed to ana...
Julio Saez-Rodriguez, Sebastian Mirschel, Rebecca ...
IDEAS
2000
IEEE
108views Database» more  IDEAS 2000»
15 years 4 months ago
Plug and Play with Query Algebras: SECONDO-A Generic DBMS Development Environment
We present SECONDO, a new generic environment supporting the implementation of database systems for a wide range of data models and query languages. On the one hand, this framewor...
Stefan Dieker, Ralf Hartmut Güting
TVLSI
2008
152views more  TVLSI 2008»
14 years 11 months ago
MMV: A Metamodeling Based Microprocessor Validation Environment
With increasing levels of integration of multiple processing cores and new features to support software functionality, recent generations of microprocessors face difficult validati...
Deepak Mathaikutty, Sreekumar V. Kodakara, Ajit Di...