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ICCD
2006
IEEE
157views Hardware» more  ICCD 2006»
15 years 7 months ago
Dynamic Co-Processor Architecture for Software Acceleration on CSoCs
By integrating one or more (hard or soft) CPU core on the chip, new generation platform FPGAs have become configurable systems on a chip (CSoC) that support a combined software an...
Abhishek Mitra, Zhi Guo, Anirban Banerjee, Walid A...
CLUSTER
2009
IEEE
14 years 8 months ago
MITHRA: Multiple data independent tasks on a heterogeneous resource architecture
With the advent of high-performance COTS clusters, there is a need for a simple, scalable and faulttolerant parallel programming and execution paradigm. In this paper, we show that...
Reza Farivar, Abhishek Verma, Ellick Chan, Roy H. ...
ICPP
2009
IEEE
15 years 5 months ago
Speeding Up Distributed MapReduce Applications Using Hardware Accelerators
—In an attempt to increase the performance/cost ratio, large compute clusters are becoming heterogeneous at multiple levels: from asymmetric processors, to different system archi...
Yolanda Becerra, Vicenç Beltran, David Carr...
ASPLOS
2010
ACM
15 years 3 months ago
An asymmetric distributed shared memory model for heterogeneous parallel systems
Heterogeneous computing combines general purpose CPUs with accelerators to efficiently execute both sequential control-intensive and data-parallel phases of applications. Existin...
Isaac Gelado, Javier Cabezas, Nacho Navarro, John ...
VRML
1997
ACM
15 years 2 months ago
V-COLLIDE: Accelerated Collision Detection for VRML
Collision detection is essential for many applications involving simulation, behavior and animation. However, it has been regarded as a computationallydemanding task and is often ...
Thomas C. Hudson, Ming C. Lin, Jonathan D. Cohen, ...