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SOSP
2001
ACM
16 years 3 months ago
Building a Robust Software-Based Router Using Network Processors
Recent efforts to add new services to the Internet have increased interest in software-based routers that are easy to extend and evolve. This paper describes our experiences using...
Tammo Spalink, Scott Karlin, Larry L. Peterson, Yi...
ISVLSI
2008
IEEE
173views VLSI» more  ISVLSI 2008»
16 years 19 days ago
Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques
The evolution of deep submicron technologies allows the development of increasingly complex Systems on a Chip (SoC). However, this evolution is rendering less viable some well-est...
Julian J. H. Pontes, Matheus T. Moreira, Rafael So...
ANSS
2007
IEEE
16 years 18 days ago
The JMT Simulator for Performance Evaluation of Non-Product-Form Queueing Networks
This paper describes JSIM: the simulation module of the Java Modelling Tools (JMT), an open-source fully-portable Java suite for capacity planning studies. The simulator has been ...
Marco Bertoli, Giuliano Casale, Giuseppe Serazzi
IPPS
2006
IEEE
16 years 8 days ago
The robot software communications architecture (RSCA): embedded middleware for networked service robots
In this paper, we present a robot middleware technology named Robot Software Communications Architecture (RSCA) for its use in networked home service robots. The RSCA provides a s...
Seongsoo Hong, Jaesoo Lee, Hyeonsang Eom, Gwangil ...
DSD
2003
IEEE
138views Hardware» more  DSD 2003»
15 years 11 months ago
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient t...
Tang Lei, Shashi Kumar