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ISVLSI
2002
IEEE
109views VLSI» more  ISVLSI 2002»
15 years 4 months ago
A Network on Chip Architecture and Design Methodology
We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NO...
Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnn...
INFOCOM
2003
IEEE
15 years 5 months ago
Using Switched Delay Lines for Exact Emulation of FIFO Multiplexers with Variable Length Bursts
—It has been studied extensively in the literature how one achieves exact emulation of First In First Out (FIFO) multiplexers for fixed size cells (or packets) using optical cro...
Cheng-Shang Chang, Duan-Shin Lee, Chao-Kai Tu
HOTI
2005
IEEE
15 years 5 months ago
Design and Implementation of a Content-Aware Switch Using a Network Processor
Cluster based server architectures have been widely used as a solution to overloading in web servers because of their cost effectiveness, scalability and reliability. A content aw...
Li Zhao, Yan Luo, Laxmi N. Bhuyan, Ravishankar R. ...
CN
2004
110views more  CN 2004»
14 years 11 months ago
TCP and UDP performance for Internet over optical packet-switched networks
A strong candidate for the future Internet core is optical packet-switched (OPS) network. In this paper, we study the impact of mechanisms as employed in OPS networks on the perfo...
Jingyi He, S.-H. Gary Chan
DATE
2009
IEEE
122views Hardware» more  DATE 2009»
15 years 6 months ago
A hybrid packet-circuit switched on-chip network based on SDM
—In this paper, we propose a novel on-chip communication scheme by dividing the resources of a traditional packet-switched network-on-chip between a packet-switched and a circuit...
Mehdi Modarressi, Hamid Sarbazi-Azad, Mohammad Arj...