199 search results - page 10 / 40 » Switching Activity Minimization in Combinational Logic Desig... |
106
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ICCAD
1997
IEEE
15 years 3 months ago
1997
IEEE
Traditional synthesis techniques optimize CMOS circuits in two phases i) logic minimization and ii) library mapping phase. Typically, the structures and the sizes of the gates in ...
80
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BSN
2006
IEEE
15 years 5 months ago
2006
IEEE
This paper introduces an encapsulated sensor node that is devised to monitor and record motion patterns over long, quotidian periods of time with potential application in psycholo...
TVLSI
2002
14 years 11 months ago
2002
Simultaneous switching noise (SSN) has become an important issue in the design of the internal on-chip power distribution networks in current very large scale integration/ultra lar...
109
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ICCD
2006
IEEE
15 years 8 months ago
2006
IEEE
— Leakage power dissipation becomes a dominant component in operation power in nanometer devices. This paper describes a design methodology to implement runtime power gating in a...
PLILP
1994
Springer
15 years 3 months ago
1994
Springer
We present the design and the implementation of clp(B): a boolean constraint solver inside the Constraint Logic Programming paradigm. This solver is based on local propagation meth...