199 search results - page 20 / 40 » Switching Activity Minimization in Combinational Logic Desig... |
ISLPED
2004
ACM
15 years 5 months ago
2004
ACM
In this paper we investigate the statistics of multiplier operands and identify two characteristics of their distribution that have important consequences for the design of low po...
DAC
1999
ACM
15 years 4 months ago
1999
ACM
: In this work we propose a technique for spatial and temporal partitioning of a logic circuit based on the nodes activity computed by using a simulation at an higher level of ion....
ICCAD
2001
IEEE
15 years 8 months ago
2001
IEEE
In this paper, we present novel algorithms that effectively combine physical layout and early logic synthesis to improve overall design quality. In addition, we employ partitionin...
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ICCAD
1995
IEEE
15 years 3 months ago
1995
IEEE
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...
PATMOS
2005
Springer
15 years 5 months ago
2005
Springer
The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed...