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ISLPED
2007
ACM
138views Hardware» more  ISLPED 2007»
15 years 1 months ago
Power optimal MTCMOS repeater insertion for global buses
This paper addresses the problem of power-optimal repeater insertion for global buses in the presence of crosstalk noise. MTCMOS technique by inserting high-Vth sleep transistors ...
Hanif Fatemi, Behnam Amelifard, Massoud Pedram
ICCD
2005
IEEE
120views Hardware» more  ICCD 2005»
15 years 8 months ago
Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis
: Power consumption in datapath modules due to redundant switching is an important design concern for high-performance applications. Operand isolation schemes are adopted to reduce...
Nilanjan Banerjee, Arijit Raychowdhury, Swarup Bhu...
VLSID
2005
IEEE
89views VLSI» more  VLSID 2005»
16 years 2 days ago
Power Optimization in Current Mode Circuits
We propose a method to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current comparators. First, we present ...
M. S. Bhat, H. S. Jamadagni
FPGA
2005
ACM
122views FPGA» more  FPGA 2005»
15 years 5 months ago
Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability
Vdd-programmable FPGAs have been proposed recently to reduce FPGA power, where Vdd levels can be customized for different circuit elements and unused circuit elements can be powe...
Yan Lin, Fei Li, Lei He
DAC
2003
ACM
15 years 5 months ago
Low-power design methodology for an on-chip bus with adaptive bandwidth capability
This paper describes a low-power design methodology for a bus architecture based on hybrid current/voltage mode signaling for deep sub-micrometer on-chip interconnects that achiev...
Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III