199 search results - page 24 / 40 » Switching Activity Minimization in Combinational Logic Desig... |
ASAP
2004
IEEE
15 years 3 months ago
2004
IEEE
In this paper, we present the design of a carry skip adder that achieves low power dissipation and high-performance operation. The carry skip adder's delay and power dissipat...
105
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ASPDAC
2006
ACM
15 years 5 months ago
2006
ACM
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...
DATE
2008
IEEE
15 years 6 months ago
2008
IEEE
We present Low Power Illinois scan architecture (LPILS) to achieve power dissipation and test data volume reduction, simultaneously. By using the proposed scan architecture, dynam...
ISWC
2000
IEEE
15 years 4 months ago
2000
IEEE
If a wearable device can register what the wearer is currently doing, it can anticipate and adjust its behavior to avoid redundant interaction with the user. However, the relevanc...
DFT
2002
IEEE
15 years 4 months ago
2002
IEEE
A novel approach for reducing power consumption in checkers used for concurrent error detection is presented. Spatial correlations between the outputs of the circuit that drives t...